Wafer fabrication is the process by which integrated circuits (ICs) are manufactured. It is basically a process by which a silicon wafer substrate is repeatedly coated, etched and rinsed to form ICs. The wafer is then cut to separate the ICs, which may then be molded into packages for mounting on circuit boards or the like.
Wafer fabrication is an imperfect process subject to manufacturing variations and defects, however slight they may be. A highly competitive wafer fabrication industry pays a great deal of attention to the occurrence and impact of these variations and defects, some of which can lead to quantities of wafers being deemed unusable. The percentage of wafers in a particular batch that are useable is referred to as yield. Yield is particularly likely to decline when fabrication is carried out under extreme conditions or with extreme fabrication parameters, otherwise known as process corners.
The IC industry is largely demand driven, and consequently, wafer fabrication tends to be carried out with specific end products and production yield in mind. Accordingly, the industry has developed a multitude of tests that narrowly identify sub-optimal wafer fabrication, allowing IC manufacturers to more precisely direct their wafer manufacturing and inventory. Manufacturing defects bringing a wafer below the threshold of usability is known as yield impact. Yield is ideally 100%, but can practically be much lower with respect to certain wafer products.
Many IC manufacturers conservatively manage yield by applying more strict fabrication targets with an expectation of some natural variance, and sometimes a violation, of those targets. A “derating factor” performs this function. The derating factor is a buffer against inherent variation in the wafer fabrication process. The conservative approach is common practice in IC design and wafer fabrication and has proven effective preventing yield loss.